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? semiconductor components industries, llc, 2013 march, 2013 ? rev. 2 1 publication order number: NCV70501/d NCV70501 micro-stepping motor driver introduction NCV70501 is a micro ? stepping stepper motor driver for bipolar stepper motors. the chip is connected through i/o pins and an spi interface with an external microcontroller. the NCV70501 contains a current ? translation table and takes the next micro ? step depending on the clock signal on the ?nxt? input pin and the status of the ?dir? (= direction) register or input pin. the chip provides an error message if stall, an electrical error or an elevated junction temperature is detected. it is using a proprietary pwm algorithm for reliable current control. NCV70501 is fully compatible with the automotive voltage requirements and is ideally suited for general ? purpose low current range stepper motor applications in the automotive, industrial, medical, and marine environment. features ? dual h ? bridge for 2 ? phase stepper motors ? programmable peak ? current up to 300 ma ? on ? chip current translator ? spi interface with daisy chain capability ? 6 step modes from full ? step up to 16 micro ? steps ? fully integrated current ? sensing and current ? regulation ? on chip stall detection ? pwm current control with automatic selection of fast and slow decay ? fixed pwm frequency ? active fly ? back diodes ? full output protection and diagnosis ? thermal (warning and) shutdown ? compatible with 3.3 v microcontrollers, 5 v tolerant inputs, 5 v tolerant open drain outputs ? reset function ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable ? these devices are pb ? free and are rohs compliant http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. ordering information pinout 9 15 16 1 3 4 gnd tst gnd motx p 13 14 11 10 12 5 6 7 8 2 NCV70501 motx n moty n moty p di clk nxt dir vbb do csb errb rhb marking diagram soic ? 16 case 751b NCV70501 ? 2g awlyww a = assembly location wl = wafer lot y = year ww = work week g = pb ? free package
NCV70501 http://onsemi.com 2 tsd spi otp timebase por di do clk nxt dir band ? gap NCV70501 logic & registers translator vbb p w m i ? sense emc p w m i ? sense emc gnd motxp motxn motyp motyn stall open / short tst internal voltage regulator 3.3 v errb rhb figure 1. block diagram NCV70501 csb table 1. pin list and description name pin description do 1 spi data output csb 2 spi chip select input di 3 spi data input gnd 4 ground clk 5 spi clock input nxt 6 next micro ? step input dir 7 direction input errb 8 error output rhb 9 run/hold current selection input motyn 10 negative end of phase y coil output motyp 11 positive end of phase y coil output vbb 12 voltage supply input gnd 13 ground motxn 14 negative end of phase x coil output motxp 15 positive end of phase x coil output tst 16 test pin input (to be tied to ground in normal operation)
NCV70501 http://onsemi.com 3 device ordering information part number temperature range package type peak current shipping ? NCV70501dw002g* ? 40 c ? 125 c soic ? 16, 150 mil (pb ? free) 300 ma tube NCV70501dw002r2g* ? 40 c ? 125 c soic ? 16, 150 mil (pb ? free) 300 ma tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *qualified for automotive applications. table 2. absolute maximum ratings symbol parameter min max unit v bb analog dc supply voltage (note 1) ? 0.3 +36 v v esd electrostatic discharges on component level (note 2) ? 2 +2 kv t strg storage temperature ? 55 +160 c t j junction temperature (note 3) ? 50 +175 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. for limited time < 0.5 s. 2. human body model (100 pf via 1.5 k , according to jedec eia ? jesd22 ? a114 ? b). 3. circuit functionality not guaranteed. table 3. thermal resistance package junction ? to ? ambient unit 1s0p board 2s0p board 2s2p board soic ? 16 96 81 72 k/w equivalent schematics the following figure gives the equivalent schematics of the user relevant inputs and outputs. the diagrams are simplified representations of the circuits used. vdd vbb digital in ipd mot out digital out errb, do motxp, motxn, motyn, figure 2. input and output equivalent diagram motyp di, clk nxt, dir rhb, csb
NCV70501 http://onsemi.com 4 electrical specification recommended operating conditions operating ranges define the limits for functional operation and parametric characteristics of the device. a mission profile (note 5) is a substantial part of the operation conditions, hence the customer must contact on semiconductor in order to mutually agree in writing on the allowed missions profile(s) in the application. note that the functionality of the chip outside these operating ranges is not guaranteed. operating outside the recommended operating ranges for extended periods of time may affect device reliability. table 4. operating ranges symbol parameter min max unit v bb analog dc supply +6 +29 v t j junction temperature ? 40 +145 (note 4) c v digio digital i/os voltage 0 5.5 v 4. operating above thermal warning level is limited in time. 5. a mission profile describes the application specific conditions such as, but not limited to, the cumulative operating conditi ons over life time, the system power dissipation, the system?s environmental conditions, the thermal design of the customer?s system, the modes, in which the device is operated by the customer, etc.
NCV70501 http://onsemi.com 5 table 5. dc parameters the dc parameters are given for v bb and t j in the recommended operating ranges unless otherwise specified. convention: currents flowing into the circuit are defined as positive. symbol pin(s) parameter remark/test conditions min typ max unit supply inputs v bb v bb nominal operating supply range 6 29 v i bb total current consumption (note 9) unloaded outputs 15 ma i bbs sleep current (note 10) 90 150 a motordriver i mdmax (peak) motxp motxn motyp motyn max peak current through motor coil in normal operation 300 ma i mdabs absolute error on coil current at i mdmax, peak = 300 ma ? 12 12 % i mdrel error on current ratio i coilx / i coily at i mdmax, peak = 300 ma ? 9 9 % r ls on resistance low side driver, high current range, ambient temperature (note 11) v bb = 12 v, t j = 27 c 1.3 on resistance low side driver, high current range, high temperature v bb = 12 v, t j = 150 c 2.7 3.8 r hs on resistance high side driver, high current range, ambient temperature (note 11) v bb = 12 v, t j = 27 c 2.0 on resistance high side driver, high current range, high temperature v bb = 12 v, t j = 150 c 4.1 5.8 r mpd motor pin pulldown resistance hiz mode 70 k logic inputs v inl di, clk nxt, dir rhb logic low input level, max tested at 1 mhz frequency 0.8 v v inh logic high input level, min tested at 1 mhz frequency 2.4 v i inl logic low input level, max tested at 1 mhz frequency ? 1 a i inh logic high input level, max tested at 1 mhz frequency 4 a v inl csb logic low input level, max tested at 1 mhz frequency 0.8 v v inh logic high input level, min tested at 1 mhz frequency 2.4 v i inl logic low input level, max (note 8) tested at 1 mhz frequency ? 50 a i inh logic high input level, max (note 8) tested at 1 mhz frequency 1 a r pd tst0 internal pulldown resistor 3 9 k logic outputs v olmax do output voltage when sinking 8 ma 0.4 v v ohmax maximum drain voltage pin in open drain state 5.5 v i olmax maximum allowed drain current 8 ma v olmax errb output voltage when sinking 8 ma 0.4 v v ohmax maximum drain voltage pin in open drain state 5.5 v i olmax maximum allowed drain current 8 ma thermal warning and shutdown t tw thermal warning 145 c t tsd (notes 6, 7) thermal shutdown t tw + 20 c 6. no more than 100 cumulated hours in life time above t tw. 7. thermal shutdown is derived from thermal warning. 8. csb has an internal weak pullup resistor of 100 k . 9. dynamic current is with oscillator running, all analogue cells active. coil currents 0 ma, spi active, errb inactive, no floa ting inputs, tst input tied to gnd. 10. all analog cells in powerdown. logic powered, no clocks running. all outputs unloaded, no floating inputs. 11. characterization value, not measured in production.
NCV70501 http://onsemi.com 6 table 6. ac parameters the ac parameters are given for v bb and temperature in their operating ranges. symbol pin(s) parameter remark/test conditions min typ max unit internal oscillator f osc frequency of internal oscillator 7 8 9 mhz motordriver f pwm motxx pwm frequency derived from internal oscillator 19.9 22.8 25.7 khz t ocdet motxx open coil detection with pwm = 100% derived from internal oscillator 50 ms t brise motxx turn ? on transient time, 10% to 90%, i md = 200 ma spi bit emc[1,0] = 00 130 ns spi bit emc[1,0] = 01 180 spi bit emc[1,0] = 10 270 t bfall motxx turn ? off transient time, 90% to 10%, i md = 200 ma spi bit emc[1,0] = 00 110 ns spi bit emc[1,0] = 01 150 spi bit emc[1,0] = 10 230 digital outputs t h2l do errb output fall ? time (90% to 10%) from v inh to v inl capacitive load 200pf and pullup resistor of 1.5 k 50 ns hard reset function t hr_trig dir hard reset trigger time see hard reset function 5 200 s t hr_dr dir hard reset dir pulse width 2.5 t hr_trig ? 2.5 s t hr_set rhb rhb setup time 5 ms t hrerr errb hard reset error indication 1 ms t csb_with csb csb wake ? up low pulse width 1 150 s t wu csb wake ? up time see sleep mode 250 s nxt/dir inputs t nxt_hi nxt nxt minimum, high pulse width (note 12) 2 s t nxt_lo nxt nxt minimum, low pulse width (note 12) 2 s t dir_set nxt, dir nxt hold time, following change of dir (note 12) 500 s t dir_hold nxt, dir nxt hold time, before change of dir (note 12) 500 s 12. characterization value, not measured in production. table 7. bemf measurement ? 5 bits adc symbol pins parameter remark/test condition min typ max unit bemf diff_r motxx bemf input range differential ? 3.75 3.75 v bemf lsb motxx bemf equivalent lsb value 125 mv bemf full_sc motxx bemf measurement full scale 3.48 3.875 4.26 v
NCV70501 http://onsemi.com 7 table 8. spi timing parameters symbol parameter min typ max unit t clk spi clock period 1 s t hi_clk spi clock high time 200 ns t clkrise spi clock rise time 1 s t clkfall spi clock fall time 1 s t lo_clk spi clock low time 200 ns t set_di di set up time, valid data before rising edge of clk 50 ns t hold_di di hold time, hold data after rising edge of clk 50 ns t hi_csb csb high time 2.5 s t set_csb_lo csb set up time, csb low before rising edge of clk (note 13) 1 s t clk_csb_hi csb set up time, csb high after rising edge of clk 200 ns t del_csb_do do delay time, do settling time after csb low (note 14) 250 ns t del_clk_do do delay time, do settling time after clk low (note 14) 100 ns 13. after leaving sleep mode an additional wait time of 250 s is needed before pulling csb low. 14. specified for a capacitive load 10 pf and a pullup resistor of 1.5 k . di valid 0.8vcc 0.8vcc t set_di t hold _di t hi_clk t clk clk cs t set_csb_lo t clk_csb _hi t hi_csb valid 0.8vcc ????? ????? ?????? ?????? ????? ????? ????? ????? ????? ????? figure 3. spi timing
NCV70501 http://onsemi.com 8 typical application schematic the application schematic below shows typical connections for applications with low axis counts and/or with software spi implementation. for applications with many stepper motor drivers, some ?minimal wiring? examples are shown at the last sections of this datasheet. figure 4. typical application schematic NCV70501 ncv 70501 gnd clk di do nxt dir motxp motxn motyp motyn m v bat vbb 22 uf c2 c1 100 nf uc d1 v dd r1 r2 errb rhb csb table 9. external components list and description component function typical value tolerance unit c1 v bb buffer capacitor (note 15) 22 ? 20 +80% f c2 v bb decoupling capacitor 100 ? 20 +80% nf r1 , r2 pullup resistor 1...5 10% k d1 optional reverse protection diode e.g. ss16 15. low esr < 4 , mounted as close as possible to the NCV70501. the total decoupling capacitance value has to be chosen properly to reduce the supply voltage ripple and to avoid em emission. functional description h ? bridge drivers with pwm control two h ? bridges are integrated to drive a bipolar stepper motor. each h ? bridge consists of two low ? side n ? type mosfet switches and two high ? side p ? type mosfet switches. one pwm current control loop with on ? chip current sensing is implemented for each h ? bridge. depending on the desired current range and the micro ? step position at hand, the r ds(on) of the low ? side transistors will be adapted to maintain current ? sense accuracy. a comparator compares continuously the actual winding current with the requested current and feeds back the information to generate a pwm signal, which turns on/off the h ? bridge switches. the switching points of the pwm duty ? cycle are synchronized to the on ? chip pwm clock. for each output bridge the pwm duty cycle is measured and stored in two appropriate status registers of the motor controller. the pwm frequency will not vary with changes in the supply voltage. also variations in motor ? speed or load ? conditions of the motor have no effect. there are no external components required to adjust the pwm frequency. in order to avoid large currents through the h ? bridge switches, it is guaranteed that the top ? and bottom ? switches of the same half ? bridge are never conductive simultaneously (interlock delay).
NCV70501 http://onsemi.com 9 in order to reduce the radiated/conducted emission, voltage slope control is implemented in the output switches. two bits in spi control register 3 allow adjustment of the voltage slopes. a protection against shorts on motor lines is implemented. when excessive voltage is sensed across a mosfet for a time longer than the required transition time, then the mosfet is switched ? off. motor enable ? disable the h ? bridges and pwm control can be disabled (high ? impedance state) by means of a bit in the spi control registers. =0 will only disable the drivers and will not impact the functions of nxt, dir, rhb, spi bus, etc. the h ? bridges will resume normal pwm operation by writing =1 in the spi register. pwm current control is then enabled again and will regulate current in both coils corresponding with the position given by the current translator. automatic forward and slow ? fast decay the pwm generation is in steady ? state using a combination of forward and slow ? decay. for transition to lower current levels, fast ? decay is automatically activated to allow high ? speed response. the selection of fast or slow decay is completely transparent for the user and no additional parameters are required for operation. icoil 0 t forward & slow decay forward & slow decay fast decay & forward actual value set value t pwm figure 5. forward and slow/fast decay pwm pwm duty cycle measurement for both motor windings the actual pwm duty cycle is measured and stored in two status registers. the duty cycle values are a representation of the applied average voltage to the motor windings to achieve and maintain the actual set point current. figure 6 gives an example of the duty cycle representation. pwm voltage icoil 0 t set value 40% 40% 40% ? 48% ? 38% ? 40% pwm value figure 6. pwm duty cycle measurement
NCV70501 http://onsemi.com 10 automatic duty cycle adaptation if during regulation the set point current is not reached before 75% of t pwm , the duty cycle of the pwm is adapted automatically to > 50% (top regulation) to maintain the requested average current in the coils. this process is completely automatic and requires no additional parameters for operation. the state of the duty cycle adaptation mode is represented in the t/b bits of the appropriate status registers for both motor windings x and y. figure 7 gives a representation of the duty cycle adaptation. actual value duty cycle < 50% duty cycle > 50% duty cycle < 50% |icoil| set value t pwm bit t/b bottom reg bit t/b = 0 top reg. bit t/b = 1 bottom reg . bit t/b = 0 0 figure 7. automatic duty cycle adaptation step translator step mode the step translator provides the control of the motor by means of spi register step mode: sm[2:0], spi bits dirp, rhbp and input pins dir (direction of rotation), rhb (run/hold of motor) and nxt (next pulse). it is translating consecutive steps in corresponding currents in both motor coils for a given step mode. one out of six possible stepping modes can be selected through spi ? bits sm[2:0]. after power ? on or hard reset, the coil ? current translator is set to the default to 1/16 micro ? stepping at position ?8*? . when remaining in the default step mode, subsequent translator positions are all in the same column and increased or decreased with 1. table 10 lists the output current versus the translator position. when the micro ? step resolution is reduced, then the corresponding least ? significant bits of the translator position are set to ?0?. this means that the position in the current table moves to the right. if there is no adjacent allowed step on the same line, then the position pointer will also move upwards or downwards (depending on the dir state) in the table to arrive at the corresponding position after one following nxt pulse when dir is ?1? or after two following next pulses when dir = ?0?. when the micro ? step resolution is increased, then the corresponding least ? significant bits of the translator position are added as ?0?: the micro ? step position moves to the left on the same row.
NCV70501 http://onsemi.com 11 table 10. circular translator table msp[5:0] step mode (sm[2:0]) % of i max msp[5:0] step mode (sm[2:0]) % of i max 000 001 010 011 coil y coil x 000 001 010 011 coil y coil x 1/16 1/8 1/4 1/2 1/16 1/8 1/4 1/2 000 000 0 0 0 0 0,0 100,0 100 000 32 16 8 4 0,0 ? 100, 0 000 001 1 ? ? ? 9,8 99,5 100 001 33 ? ? ? ? 9,8 ? 99,5 000 010 2 1 ? ? 19,5 98,1 100 010 34 17 ? ? ? 19,5 ? 98,1 000 011 3 ? ? ? 29,0 95,7 100 011 35 ? ? ? ? 29,0 ? 95,7 000 100 4 2 1 ? 38,3 92,4 100 100 36 18 9 ? ? 38,3 ? 92,4 000 101 5 ? ? ? 47,1 88,2 100 101 37 ? ? ? ? 47,1 ? 88,2 000 110 6 3 ? ? 55,6 83,1 100 110 38 19 ? ? ? 55,6 ? 83,1 000 111 7 ? ? ? 63,4 77,3 100 111 39 ? ? ? ? 63,4 ? 77,3 001 000 8 (*) 4 2 1 70,7 70,7 101 000 40 20 10 5 ? 70,7 ? 70,7 001 001 9 ? ? ? 77,3 63,4 101 001 41 ? ? ? ? 77,3 ? 63,4 001 010 10 5 ? ? 83,1 55,6 101 010 42 21 ? ? ? 83,1 ? 55,6 001 011 11 ? ? ? 88,2 47,1 101 011 43 ? ? ? ? 88,2 ? 47,1 001 100 12 6 3 ? 92,4 38,3 101 100 44 22 11 ? ? 92,4 ? 38,3 001 101 13 ? ? ? 95,7 29,0 101 101 45 ? ? ? ? 95,7 ? 29,0 001 110 14 7 ? ? 98,1 19,5 101 110 46 23 ? ? ? 98,1 ? 19,5 001 111 15 ? ? ? 99,5 9,8 101 111 47 ? ? ? ? 99,5 ? 9,8 010 000 16 8 4 2 100,0 0,0 110 000 48 24 12 6 ? 100,0 0,0 010 001 17 ? ? ? 99,5 ? 9,8 110 001 49 ? ? ? ? 99,5 9,8 010 010 18 9 ? ? 98,1 ? 19,5 110 010 50 25 ? ? ? 98,1 19,5 010 011 19 ? ? ? 95,7 ? 29,0 110 011 51 ? ? ? ? 95,7 29,0 010 100 20 10 5 ? 92,4 ? 38,3 110 100 52 26 13 ? ? 92,4 38,3 010 101 21 ? ? ? 88,2 ? 47,1 110 101 53 ? ? ? ? 88,2 47,1 010 110 22 11 ? ? 83,1 ? 55,6 110 110 54 27 ? ? ? 83,1 55,6 010 111 23 ? ? ? 77,3 ? 63,4 110 111 55 ? ? ? ? 77,3 63,4 011 000 24 12 6 3 70,7 ? 70,7 111 000 56 28 14 7 ? 70,7 70,7 011 001 25 ? ? ? 63,4 ? 77,3 111 001 57 ? ? ? ? 63,4 77,3 011 010 26 13 ? ? 55,6 ? 83,1 111 010 58 29 ? ? ? 55,6 83,1 011 011 27 ? ? ? 47,1 ? 88,2 111 011 59 ? ? ? ? 47,1 88,2 011 100 28 14 7 ? 38,3 ? 92,4 111 100 60 30 15 ? ? 38,3 92,4 011 101 29 ? ? ? 29,0 ? 95,7 111 101 61 ? ? ? ? 29,0 95,7 011 110 30 15 ? ? 19,5 ? 98,1 111 110 62 31 ? ? ? 19,5 98,1 011 111 31 ? ? ? 9,8 ? 99,5 111 111 63 ? ? ? ? 9,8 99,5 *default position after reset of the translator position.
NCV70501 http://onsemi.com 12 besides the micro ? step modes listed above, also two full step modes are implemented. full step mode 1 activates always only one coil at a time, whereas mode 2 always keeps 2 coils active. the table below lists the output current versus the translator positions for these cases and figure 8 shows the projection on a square. changing between micro ? step mode and full step modes follows a similar scheme as changes between micro ? step modes. changing from one full step mode to another full step mode will always result in a ?45deg step ? back or forward? depending on the dir bit. for example: in the table below, when changing full step mode (positioner is on a particular row and full step column), then the new full step location will be one row above or below in the adjacent ?full step column?. the step ? back and forward is executed after the nxt pulse. example change fs1 ? >fs2 ? >fs1 (cw direction): msp=?100 000?(fs1) => new msp=?011 000?(fs2) => new msp=?010 000?(fs1) table 11. square translator table for full step msp[5:0] step mode ( sm[2:0] ) % of imax 101 111 coil x coil y full step1 full step2 000 000 0 ? 100 0 001 000 ? 0 71 71 010 000 1 ? 0 100 011 000 ? 1 ? 71 71 100 000 2 ? ? 100 0 101 000 ? 2 ? 71 ? 71 110 000 3 ? 0 ? 100 111 000 ? 3 71 ? 71 i y i x 1 i y i x i y i x 0 2 3 0 1 2 3 1 23 0 figure 8. translator table: circular and square 1/4 th micro ? step sm[2:0] = 010 full step1 sm[2:0] = 101 full step2 sm[2:0] = 111 translator position the translator position can be read in the spi register . this is a 6 ? bit number equivalent to the 1/16 th micro ? step from table 10: circular translator table. the translator position is updated immediately following a next micro ? step trigger (see figure 9). nxt update translator position update translator position figure 9. translator position timing diagram
NCV70501 http://onsemi.com 13 direction the direction of rotation is selected by means of input pin dir and its ?polarity bit? (spi register). the polarity bit allows changing the direction of rotation by means of only spi commands instead of the dedicated input pin. direction = dir ? pin exor positive direction of rotation means counter ? clockwise rotation of electrical vector ix + iy. also when the motor is disabled (=0), both the dir pin and will have an effect on the positioner. the logic state of the dir pin is visible as a flag in spi status register. next micro ? step trigger positive edges on the nxt input ? or activation of the ?nxt pushbut ton? in the spi input register ? will move the motor current one step up/down in the translator table. the bit in spi is used to move positioner one (micro ? )step by means of only spi commands. if the bit is set to ?1?, it is reset automatically to ?0? after having advanced the positioner with one micro ? step. trigger ?next micro ? step? = (positive edge on nxt ? pin) or (=1) ? also when the motor is disabled (=0), nxt/dir/rhb functions will move the positioner according to the logic. ? in order to be sure that both the nxt pin and the spi command are individually attended, the following non overlapping zone has to be respected. in this case it is guaranteed that both triggers will have effect (2 steps are taken). nxt csb t csb _lo_width 0.8vcc 0.2vcc figure 10. nxt input nonoverlapping zone with the spi command for control by means of i/o?s, the nxt ? and dir pin operation should be in a non ? overlapped way. see also the timing diagram below (refer to the ac table for the timing values). on the other hand, both spi bits and can change state at the same time in the same spi command: the next micro ? step will be applied in the new direction. ?? ?? ?? ??????? ??????? ??????? dir nxt valid t nxt_hi t nxt_lo t dir_set t dir_hold 0.5vcc figure 11. nxt ? input timing diagram irun, ihold and ?run / not hold? mode the rhb input pin and it?s ?polarity bit? (spi register) allow to switch the driver between ?run mode? and ?hold mode?. ?run mode? = not(?hold mode?) = rhb pin exor ? in ?run mode?, the current translator table is stepped through based on the ?nxt & dir? commands. the amplitude of the motor current (=imax) is set by spi control register ?irun[3:0]?. ? in ?hold mode?, nxt & dir will have no effect and the position in the current translator table is maintained. the motor current amplitude is set by spi control register ?ihold[3:0]?. the run and hold current settings correspond to the following current levels: table 12. irun and ihold reference values (4 ? bit) register value peak motor current irun (ma) peak motor current ihold (ma) 0 15 0* 1 27 15 2 48 27 3 87 48 4 100 87 5 115 100 6 132 115 7 152 132 8 174 152 9 200 174 a 230 200 b 300 230 *during hold with a hold current of 0 ma the stall and motion de- tection and the open coil detection are disabled. the pwm duty cycle registers will present 0% duty cycle.
NCV70501 http://onsemi.com 14 whenever irun[3:0] or ihold[3:0] is changed, the new coil currents will be updated immediately at the next pwm period. in case the motor is disabled (=0), the logic is functional and both rhb pin and bit will have effect on nxt/dir operation (not on the h ? bridges). when the chip is in sleep mode, the logic is not functional and as a result, the rhb pin will have no effect. the logic state of the rhb pin is visible as a flag in spi status register. note : the hard ? reset function is embedded in the ?hold mode? by means of a special sequence on the dir pin, see also (hard reset ). stall and motion detection motion detection is based on the back electromotive force (bemf or back emf) generated into the stepper driver h ? bridge. when the motor is blocked, e.g. when it hits the end ? position, t he velocity and as a result also the generated back emf, is disturbed. the NCV70501 measures the differential back emf during the current zero crossing phase and makes it available in the spi status register 3. the measurement samples are taken every pwm period and will be converted into a 5 ? bits coded word, with the following formula: bemf_code(dec) v_mot_xory_diff (v) * 5 8 * 2 5 2.41 for further reference, please see spi map and table 7 ? bemf. at the end of the current zero crossing the internal circuitry compares the last sampled value with a threshold for the stall detection. for slow speed or when a motion ends at a full step position, the end of the zero crossing is taking too long or is non ? existing. therefore, the comparison of bemf with the threshold will be done ? in the absence of a nxt trigger ? the latest at ?stall time ? out?. this time ? out is set in spi by means of and is expressed in counts of 4/f pwm (see ac table), roughly in steps of 0.2 ms. if = 0 then this time ? out is not active. if = 0 then stall detection is disabled. if the bemf signal is measured to be below the stthr level for 2 succeeding coil current zero ? crossings, then the stall bit in spi is set, the current translator table goes 135degrees in opposite direction and the errb pin is pulled low, irun is maintained. the stall bit in spi register is cleared upon read of the microcontroller, also the errb pin is inactive again. after the stall bit has been cleared, the chip will react on ?next micro ? step triggers? only when the direction changed state at least once. an additional feature of the NCV70501 is the detection of uncontrolled motion during hold. if the stall detection is enabled and the hold position is at full steps (full step mode1, 0 , 90 , 180 , 270 ) with only excitation of one coil, the NCV70501 is checking upon back emf voltages higher then the threshold. if this higher voltage is detected it indicates there is a motor movement. the stall bit in the spi register is set and the errb pin will be activated. the motion detection during hold does not work for ihold is 0a. table 13. stall threshold settings (4 ? bit) stthr[3:0] index stthr level (v) 0 disable 1 0.125 2 0.250 3 0.375 4 0.50 5 0.625 6 0.75 7 1.0 8 1.25 9 1.5 a 1.75 b 2.0 c 2.25 d 2.50 e 2.75 f 3.00 warning, error detection and diagnostics feedback thermal warning and shutdown when junction temperature is above t tw , the thermal warning bit is set (spi register ) and the errb pin is pulled low*. if junction temperature increases above thermal shutdown level, then also the flag is set, the errb pin is pulled low, the motor is disabled ( = 0) and the hardware reset is disabled. if t j < t tw level and after reading of the status of is cleared and the errb pin is released. only if the ==0 the motor can be enabled again by writing =1 in the control register 1. during the over temperature condition the hardware reset will not work until t j < t tw and the readout is done. in this way it is guaranteed that after a =1 event, the die ? temperature decreases back to the level of t tw . * remark : during the situation the motor is not disabled while the errb is pulled low. to be informed about other error situations it is recommended to poll the status registers on a regular base (time base driven by application software in the millisecond domain). over ? current detection the over ? current detection circuit monitors the load current in each activated output stage. if the load current exceeds the over ? current detection threshold, then the over ? current flag is set and the drivers are
NCV70501 http://onsemi.com 15 switched off to protect the integrated circuit. each driver stage has an individual detection bit for the n side and the p side. during a short situation the motor enable bit becomes low. the positioner, the nxt, rhb and dir stay operational. the flag (result of or ? ing the latched flags : or or or or or or or ) is reset when the microcontroller reads&resets the short circuit status flags in status registers 6 and 7. to enable the motor after a cleared short flag, =1 has to be written. depending on the bit in spi control register 3 the motor driver performs an automatic diagnostics procedure after enabling the motor (refer to the automatic diagnostics section). notes : 1. successive reading of the flags and enabling the motor in case of a short circuit condition, may lead to damage of the drivers. 2. example: shrtxpt means: short at x coil, positive output pin, top transistor. open coil detection there are two open coil detection methods used: after power up: during the power up reset state, the electronics automatically performs diagnostics for open coils and short circuit conditions. if an error situation is detected the or with the and bits are set in the spi status registers. these bits remain active during the entered sleep mode after power ? up (refer to the sleep mode section). during operation: open coil detection is based on the observation of 100 perc ent duty cycle of the pwm regulator. if in a coil 100 percent duty cycle is detected for longer than t ocdet then the related driver transistors are disabled (high ? impedance) and the appropriate bit ( or ) together with in the spi status register are set. during the stated situation the positioner and the not open coil stay functioning, as well as the motor enable bit. after reading the status of the open coil bit, the output stage concerned will become active again. remark : in order to detect an open coil, it needs to be driven without interruption during minimum t ocdet . this is typically the case during hold condition or very slow motions. spi framing error the spi transmission is continuously monitored for correct amounts of incoming data bits. if within one frame of data the number of spi clk high transitions is not equal to a multiple of 16 (16,32,48,...), then the spi error bit in the status register is set and the errb pin goes low to indicate this error to the micro controller. during this fault condition the incoming data is not loaded into the internal registers and the transmit shift register is not loaded with the requested data. the status of the spi framing error is reset by an errorless received frame requesting for the motor controller status register 0. this request will reset the spi error bit and releases the errb pin (high). error output this is an open drain output to flag a problem to the external microcontroller. the signal on this output is active low and the logic combination of: not(errb) = ( or or or or or or or (*)reset state) and not(**)sleep mode * reset state: after a power ? on or a hard ? reset, the errb is pulled low during threrr (table 8: ac parameters). ** sleep mode: in sleep mode the errb is always inactive (high). automatic diagnostics via the diagnostics enable bit in spi control register 3 an automatic diagnostics mode can be enabled. the diagnostic routine is the same as the routine in powerup situation. when automatic diagnostics is enabled, every time when the user changes the motor enable state from ?0? to ?1?, the diagnostics are performed. the dead time for this diagnostics routine is 1 ms * . *for a controlled start of the diagnostics the user has to place the motor driver in high impedance state by setting the moten bit to ?0?. after changing this bit, there is need for an additional delay time. this is needed for recirculation of the motor current. an average time of approximately 2ms is needed. this time has to be taken into account by the user. sleep mode the motor driver can be put in a low ? power consumption mode (sleep mode). the sleep mode is entered automatically after a power ? on or hard reset and can also be activated by means of spi bit . in sleep ? mode, all analog circuits are suspended in low ? power and all digital clocks are stopped: spi communication is impossible. the motor driver is disabled (even if =1), the content of all logic registers is maintained (including , and ), all logic output pins are disabled (errb has no function) and none of the input pins are functional with the exception of pin csb. only this pin can wake ? up the chip to normal mode (i.e. clear bit ) by means of a ?high ? to ? low voltage? transition. after wake ? up, some time t wu , (see ac table) is needed to restore analog and digital clocks and to bring spi communication within specification. notes: ? the hard ? reset function is disabled in sleep mode.
NCV70501 http://onsemi.com 16 ? the thermal shutdown function will be ?frozen? during sleep mode and re ? activated at wake ? up. this is important in case bit =1 was cleared already by the micro and was not ?0? yet. ? the csb low pulse width has to be within t csb_with , (see ac table) to guarantee a correct wake ? up power ? on reset, hard ? reset function after a power ? on a flag

in the spi status register is set and the errb is pulled low. the errb stays low during this reset state. the maximum power ? on reset time is given by threrr (t able 6: ac parameters). after the reset state the device enters sleep mode and the errb pin goes high to indicate the motor controller is ready for operation. by means of a specific pattern on the dir pin during the ?hold mode?, the complete digital can be reset without a power ? cycle. this so ca lled hard ? reset function is activated when during ?hold mode?, the input pin dir changes logic state ?0 ? >1 ? >0 ? >1? within t hr_trig (table 6: ac parameters). the operation of all analog circuits is suspended during the reset state of the digital. similar as for a normal power ? on, the flag

is set in the spi register after a hard ? reset and the errb pin is pulled low during threrr (table 8: ac parameters). to enable the motor controller to perform a proper self diagnosis, it is recommended that the motor is in ?hold mode? before the hard reset is generated. the minimum time (thr_set) between the beginning of ?hold mode? and the first rising edge of the dir pin is given in table 6: ac parameters. t hr_set dir rhb hold mode t hr_trig t hr_dr figure 12. hard reset timing diagram spi interface the serial peripheral interface (spi) is used to allow an external microcontroller (mcu) to communicate with the device. NCV70501 acts always as a slave and it cannot initiate any transmission. the operation of the device is configured and controlled by means of spi registers, which are observable for read and/or write from the master. the implemented spi allows connection to multiple slaves by means of both time ? multiplexing (csb per slave) and daisy ? chain (csb per group of slaves). multi ? axis connections schemes are discussed in a separate chapter below. spi transfer format and pin signals all spi commands (to di pin of NCV70501) from the micro controller consist of one ?address byte? and one ?data byte?. the address byte contains up to two addresses of each 4 bit long. these addresses are pointing to a command or requested action in a spi slave. three command ? types can be distinguished: ?write to a control register?, ?read from a control register? and ?read from a status register?. ? writing to a control register is accomplished only if the address of the target register appears in the first half of the address byte. the contents of the data ? byte will be copied in the control register. the contents of the addressed control register will be sent back by the NCV70501 in the next spi access. ? reading from a control register is accomplished by putting its address in the second half of the address byte. the data byte has no function for this command. ? reading from a status register is accomplished by putting its address either in the first or in the second half of the address byte. the data byte has no function for this command. the response (from do pin of NCV70501) on these commands is always 2 bytes long. the possible combinations of di/do and their use are summarized in the following table 14. figure 13 gives examples of the data streaming:
NCV70501 http://onsemi.com 17 table 14. spi command address, data and response structure di addr[7:4] di addr[3:0] di data[7:0] do byte1 do byte2 comment on use acr1 acr2 dicr1 docr1 docr2 control and status of cr acr1 asr1 dicr1 docr1 dosr1 control and status of sr acr1 nop dicr1 docr1 00h control and no status asr1 acr1 xxh dosr1 docr1 status of sr and cr asr1 asr2 xxh dosr1 dosr2 status of sr and sr asr1 nop xxh dosr1 00h status of sr nop acr1 xxh 00h docr1 status of cr nop asr1 xxh 00h dosr1 status of sr nop nop xxh 00h 00h dummy/placeholder with: ? acrx = address of control register x ? asrx = address of status register x ? dicrx = data input of control register x ? doxy = data output of corresponding register contents transmitted in the next spi access ? nop = register address outside range : 0h, ch, dh, eh or fh ? xxh = any byte csb acr1 ???? acr2 data for acr1 previous data example 1: write cr1, read cr1 and cr2 previous data command this is the data from command before or not valid after power up or reset data from acr1 data from acr2 next command next data data master ? > slave csb acr3 ???? acr5 data for acr3 previous data slave ? > master example 2: write cr3, read cr3 and sr5 previous data command this is the data from command before or not valid after powerup or reset data from acr3 data from asr5 next command next data data csb asr5 ???? acr7 dummy previous data example 3: read sr5 and sr8 previous data command this is the data from command before or not valid after powerup or reset data from asr5 data from asr7 next command next data data the written control registers are updated by the 70501 at the rising edge of csb the contents of the previously addressed registers are copied into the transmission shift registers at the falling edge of csb figure 13. command and data streaming of spi master ? > slave slave ? > master master ? > slave slave ? > master
NCV70501 http://onsemi.com 18 table 15. spi control registers 4 ? bit address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default after reset 1h (cr1) dirp rhbp nxtp moten sttrh[3] sttrh[2] sttrh[1] sttrh[0] 0000 0000 2h (cr2) ihold[3] ihold[2] ihold[1] ihold[0] irun[3] irun[2] irun[1] irun[0] 0000 0000 3h (cr3) reserved diagen emc[1] emc[0] slp sm[2] sm[1] sm[0] 0010 0000 4h (cr4) stto[7] stto[6] stto[5] stto[4] stto[3] stto[2] stto[1] stto[0] 0001 0000 all spi control registers have read/write access. the NCV70501 responds on every incoming byte by shifting out the data stored on the last address sent via the bus. after power on reset (por) the initial address is unknown, so in that case th e first data shifted out is undefined. note: all ?reserved? bits cannot be written to one and will always be read out as zeroes. bits definition symbol map position description dirp bit 7 ? addr_0x01 (cr1) direction control polarity (inverts the logic polarity of the related dir pin) rhbp bit 6 ? addr_0x01 (cr1) polarity of rhb pin; rhbp = 1 inverts rhb pin (hold = not( rhb xor rhbp)) nxtp bit 5 ? addr_0x01 (cr1) push button pin, generating next step in position table moten bit 4 ? addr_0x01 (cr1) enables the x y h-bridges (motor activated, either in run or in hold). stthr[3:0] bits [3:0] ? addr_0x01 (cr1) threshold level for internal stall detection algorithm; disabled when ?0?. ihold[3:0] bits [7:4] ? addr_0x02 (cr2) current amplitude in hold mode. irun[3:0] bits [3:0] ? addr_0x02 (cr2) current amplitude in run mode. diagen bit 6 ? addr_0x03 (cr3) enables automatic diagnostics at the rising edge of moten bit. emc[2:0] bits [5:4] ? addr_0x03(cr3) voltage slope defining bits for motor driver switching. three combinations are avail- able up to ?10? slp bit 3 ? addr_0x03 (cr3) places the device in sleep mode with low current consumption (when written as ?1?). note that this bit cannot read back for verification as by doing so the device will awake. sm[2:0] bits [2:0] ? addr_0x03(cr3) step mode selection (see related tables). stto[7:0] bits [7:0] ? addr_0x04(cr4) max programmed difference between two successive full step next pulse periods (timeout): after this time the bemf sample is taken to verify stall. table 16. spi status register (sr) all spi status registers have read only access, with the even parity on bit7 4 ? bit address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 comment default after reset 5h (sr1) par spi,l short,r open,r tsd,l tw,r stall,l hr,l errors x0xx xx01 6h (sr2) par rhbpin,r msp5,r msp4,r msp3,r msp2,r msp1,r msp0,r micro ? step position xx00 1000 7h (sr3) par dirpin, r bemfs, r bemf4, r bemf3, r bemf2, r bemf1, r bemf0, r input pins and bemf xx00 0000 8h (sr4) par t/bx,r signx,r pwmx4,r pwmx3,r pwmx2,r pwmx1,r pwmx0,r pwmx 0000 0000 9h (sr5) par t/by,r signy,r pwmy4,r pwmy3,r pwmy2,r pwmy1,r pwmy0,r pwmy 0000 0000 ah (sr6) par openx,l reserved reserved shrtxpb,l shrtxnb,l shrtxpt,l shrtxnt,l shortsx xx00 xxxx bh (sr7) par openy,l reserved reserved shrtypb,l shrtynb,l shrtypt,l shrtynt,l shortsy xx00 xxxx flags have ?,l? for latched information or ?,r? for real time information. all latched flags are ?cleared upon read?. all spi status registers have read access. flags have ?,l? for latched information or ?,r? for real time information. all latched flags are ?cleared upon read?. note: all ?reserved? bits will always be read out as zeroes. all status registers data i s protected by even parity.
NCV70501 http://onsemi.com 19 bits definition symbol bit position reg description par bit 7 ? addr_0x05 sr1 parity bit for sr1. spi bit 6 ? addr_0x05 sr1 spi error: no multiple of 16 rising clock edges between falling and rising edge of csb line. short bit 5 ? addr_0x05 sr1 an over current detected (common : reads if one of the shortij individual bits are set) open bit 4 ? addr_0x05 sr1 open coil x or y detected (common : reads if one of the two specific x / y open coil bits is set) tsd bit 3 ? addr_0x05 sr1 thermal shutdown flag. this situation should always be avoided in the final ap- plication by proper thermal design. tw bit 2 ? addr_0x05 sr1 thermal warning flag. the controller unit should take action before the tsd is reached (shutdown). stall bit 1 ? addr_0x05 sr1 stall detected by the internal algorithm (bemf < stthr). the feature can be dis- abled (see prev. table) hr bit 0 ? addr_0x05 sr1 reset flag: ?1? indicates that any reset has occurred (all registers content will go to por default). par bit 7 ? addr_0x06 sr2 parity bit for sr2. rhbpin bit 6 ? addr_0x06 sr2 read out of rhb pin logic status. msp[5:0] bits[5:0] ? addr_0x06 sr2 current translator micro-step position (see related table for details). par bit 7 ? addr_0x07 sr3 parity bit for sr3. dirpin bit 6 ? addr_0x07 sr3 read out of dir pin logic status. bemfs bit 5 ? addr_0x07 sr3 last bemf measured voltage has expected polarity (yes = 0, no = 1 means opposite sign). bemf[4:0] bits [4:0] ? addr_0x07 sr3 bemf measured value code. see formula in stall detection section for details. par bit 7 ? addr_0x08 sr4 parity bit for sr4. t/bx bit 6 ? addr_0x08 sr4 pwm regulation mode on x coil (regulation on top = 1 or bottom = 0) signx bit 5 ? addr_0x08 sr4 pwm sign for x coil regulation (?0? = positive, ?1? = negative) pwmx[4:0] bits [4:0] ? addr_0x08 sr4 pwm duty cycle value for coil x (proportional: 100% corresponds to 31dec) par bit 7 ? addr_0x09 sr5 parity bit for sr5. t/by bit 6 ? addr_0x09 sr5 pwm regulation mode on y coil (regulation on top = 1 or bottom = 0) signy bit 5 ? addr_0x09 sr5 pwm sign for y coil regulation (?0? = positive, ?1? = negative) pwmy[4:0] bits [4:0] ? addr_0x09 sr5 pwm duty cycle value related to coil y (proportional: 100% corresponds to 31dec) par bit 7 ? addr_0x0a sr6 parity bit for sr6. openx bit 6 ? addr_0x0a sr6 open coil x detected. reserved bits [5:4] ? addr_0x0a sr6 reserved, will be read as zeroes. shrtxpb bit 3 ? addr_0x0a sr6 short circuit detected at xp pin towards ground (bottom). shrtxnb bit 2 ? addr_0x0a sr6 short circuit detected at xn pin towards ground (bottom). shrtxpt bit 1 ? addr_0x0a sr6 short circuit detected at xp pin towards supply (top). shrtxnt bit 0 ? addr_0x0a sr6 short circuit detected at xn pin towards supply (top). par bit 7 ? addr_0x0b sr7 parity bit for sr7. openy bit 6 ? addr_0x0b sr7 open coil y detected. shrtypb bit 3 ? addr_0x0b sr7 short circuit detected at yp pin towards ground (bottom). shrtynb bit 2 ? addr_0x0b sr7 short circuit detected at yn pin towards ground (bottom). shrtypt bit 1 ? addr_0x0b sr7 short circuit detected at yp pin towards supply (top). shrtynt bit 0 ? addr_0x0b sr7 short circuit detected at yn pin towards supply (top).
NCV70501 http://onsemi.com 20 application examples for multi ? axis control the wiring diagrams below show possible connections of multiple slaves to one microcontroller. in these examples, all movements of the motors are synchronized by means of a common nxt wire. the direction and run/hold activation is controlled by means of an spi bus. further i/o reduction is accomplished in case the errb is not connected. this would mean that the microcontroller operates while polling the error flags of the slaves. ultimately, one can operate multiple slaves by means of only 4 spi connections: even the nxt pin can be avoided if the microcontroller operates the motors by means of the ?nxtp? bit. nxt csb1 csb2 csb3 di/do/clk errb nxt csb di/do/clk errb nxt csb di/do/clk errb nxt csb di/do/clk errb 3 3 3 ic1 NCV70501 ic2 NCV70501 ic3 NCV70501 microcontroller ?multiplexed spi? vcc rpu csb/clk/nxt do di errb csb/clk/nxt di do errb csb/clk/nxt di do errb csb/clk/nxt di do errb 3 3 3 ic1 NCV70501 ic2 NCV70501 ic3 NCV70501 microcontroller ?daisy ? chained spi? vcc rpu figure 14. examples of wiring diagrams for multi ? axis control* csb/clk do di csb/clk di do csb/clk di do csb/clk di do 2 2 2 ic1 NCV70501 ic2 NCV70501 ic3 NCV70501 microcontroller full spi, minimal wiring figure 15. minimal wiring diagram for multi ? axis control* *this drawing does not present the hard reset interconnection. for the functionality of the hard reset function the rhb and dir pins have to be connected to the micro controller.
NCV70501 http://onsemi.com 21 electro magnetic compatibility the NCV70501 has been developed using state ? of ? the ? art design techniques for emc. the overall system performance depends on multiple aspects of the system (ic design and lay ? out , pcb design and layout ...) of which some are not solely under control of the ic manufacturer. therefore, meeting system emc requirements can only happen in collaboration with all involved parties. special care has to be taken into account with long wiring to motors and inductors. a modern methodology to regulate the current in inductors and motor windings is based on controlling the motor voltage by pwm. this low frequency switching of the battery voltage is present at the wiring towards the motor or windings. to reduce possible radiated transmission, it is advised to use twisted pair cable and/or shielded cable.
NCV70501 http://onsemi.com 22 package dimensions soic ? 16 case 751b ? 05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCV70501/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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